A phase locked loop is mainly composed of a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, a frequency divider and an automatic frequency calibration module. Frequency calibration techniques mainly fall into two categories: a closed-loop frequency calibration technique, and an open-loop frequency calibration technique. However, a calibration algorithm exerts a great influence on calibration time taken to calibrate frequency of the voltage controlled oscillator for both the closed-loop frequency calibration technique and the open-loop frequency calibration technique.
In the prior art, what is commonly adopted is a calibration algorithm which carries out successive comparison, in which if the voltage controlled oscillator is provided with an N-bit wide switched capacitor array C<N-1, 0>, the weight between each bit is 2:1, then the most times of comparisons is N-1th power of 2, and the number of calibrations will be greatly increased when N is relatively great, leading to very long calibration time. Therefore, how to reduce the calibration time taken to calibrate output frequency of the voltage controlled oscillator is a problem to be solved urgently.